Delay locked loop (DLL) circuits are often used in high-speed signaling systems to generate clock signals having precisely controlled phase offsets relative to a reference clock. FIG. 1 illustrates one such prior art signaling system including a master device 101 coupled to a N slave devices, 1031–103N, via a data path 102, and a clock generator 106 coupled to the master device 101 and the slave devices 103 via a clock line 104. A reference clock signal, CLK, generated by the clock generator 106 is used within the master device 101 to time the transmission of data and is used within the slave devices 103 to time data reception. In theory, the flight time (i.e., signal propagation time) of the clock signal on the clock line 104 is the same as the data flight time on the data path 102 so that a phase relationship between a clock edge passing by the master device 101 and data output by the master device is maintained as the clock edge and data arrive at the various slave devices 103. In reality, however, differences between clock and data path characteristics (e.g., parasitic capacitance, loading, etc.), however small, result in flight time differences (i.e., skew) between the clock and data signals. Because the width of a data eye (i.e., data valid interval) in high-speed signaling systems is extremely brief (e.g., 2 nanoseconds in the case of a 500 MHz symbol rate), even a small amount of skew may result in violation of setup and hold time requirements of sampling circuits within the slave devices and therefore lead to data sampling errors. Accordingly, in the prior art system of FIG. 1, DLL circuits are included within each of the slave devices to generate sampling clock signals that are aligned to the desired sampling instant for the slave device. This arrangement is shown in FIG. 1 by the detail view of slave device 103 which includes a DLL circuit 107 to generate a sampling clock (SCLK) and a sampling circuit 109 to sample data (thereby generating sampled data signal, SDATA) in response to the sampling clock.
FIG. 2 illustrates a prior art DLL circuit. The delay locked loop circuit includes a reference loop 121, a mix loop 123, and a sampling clock generator 125. The reference loop includes a level converter 127, delay line 129 and phase detector 131 which cooperate to generate incrementally delayed versions of a reference clock signal, referred to as phase vectors 122. The level converter converts the signaling level of the incoming reference clock signals (i.e., complementary clock pair, CLK and /CLK) from CMOS (complementary metal oxide semiconductor) to differential pair small swing (DPSS) signals. The DPSS-level clock signals are input to the delay line which is formed by a plurality of differential amplifier delay elements each of which introduces a phase delay according to a bias voltage, DCTL. The phase detector 131 adjusts the bias voltage DCTL as necessary to produce a total delay, through a selected set of the delay elements 133, equal to a full cycle of the reference clock signal, CLK. That is, the phase detector 131 compares a nominally zero degree phase vector with a nominally 360 degree phase vector and increases or decreases the bias voltage (thereby decreasing or increasing the delay of the delay line) according to whether the 360 degree phase vector lags or leads the 0 degree phase vector. The number of delay elements 133 in the delay line is such that each delay element introduces a 45 degree input-to-output delay when the 0 and 360 degree vectors are in phase alignment. Accordingly, the phase vectors 122 range from 0 to 315 degrees in 45 degree phase steps.
The mix loop 123 includes a mixer 141, level converter 143, clock tree circuit 145 and phase detector 147 which cooperate to generate a mix control signal, MCTL. The mixer receives the phase vectors 122 from the reference loop 121 and interpolates between a selected pair of the phase vectors to generate a mix clock signal 142. The mix clock signal 142 is converted from a DPSS signaling level to a CMOS signaling level by converter 143 is then passed through the clock tree circuit 145 (typically a series of amplifiers that enable fan out of multiple instances of the clock signal) to generate a feedback clock signal, FCLK. The phase detector 147 compares the feedback clock signal with the reference clock signal and generates the adjust signal according to which clock signal leads the other. For example, if the reference clock signal leads the feedback clock signal, the phase detector 147 signals the mixer 141 (i.e., by appropriate state of the adjust signal) to shift interpolation toward the leading one of the selected phase vectors (and away from the trailing phase vector), thereby advancing the phase of the feedback clock. Conversely, if the reference clock signal lags the feedback clock signal, the phase detector 147 signals the mixer to shift interpolation toward the trailing one of the selected phase vectors. If the reference clock still leads or lags the feedback clock signal after interpolation has been shifted completely to one of the selected phase vectors, a different pair of phase vectors (i.e., bounding an adjacent range of phase angles) is selected by the mixer 141.
The sampling clock generator 125 includes a mixer 149, converter 151 and clock tree circuit 153 that essentially mirror the operation of the mixer, converter and clock tree circuit within the mix loop 123 to generate a sampling clock signal, SCLK. The mixer 149 receives the mix control signal, MCTL, generated within the mix loop 123 and therefore, when an offset control signal, OCTL, indicates zero offset, performs the same interpolation operation on the same pair of selected vectors as the mixer 141. As the adjust signal is incremented and decremented, the mixer 149 tracks the operation of the mixer 141 such that the sampling clock signal tracks the feedback clock signal (i.e., the sampling clock signal and feedback clock signal have the same phase). The offset control value, OCTL, is a value that is added to a count maintained within the mixer 149 to provide a controlled, adjustable offset between the sampling clock and reference clock, thereby allowing correction of skew between the reference clock and a desired sampling instant.
FIG. 3 illustrates, in part, a prior art mixer 141 for mixing DPSS-level clock signals. The mixer 141 includes mix logic 161 and a number of differential amplifier circuits 163 (only two of which, 1631 and 1632, are shown in the simplified diagram of FIG. 3). The differential amplifiers 163 each receive respective pairs of complementary phase vectors and have output nodes that are pulled up through a common pair of load resistances, R. By this arrangement, the resultant mix clock signal, MCLK, will have a phase that is between the phases of the input phase vectors according to the bias voltages, ICTL and /ICTL, applied to the respective biasing transistors of the differential amplifiers 163. The mix logic 161 maintains a counter 171 that is incremented and decremented in response to the mix control signal, MCTL, and a pair of digital-to-analog converters (DACs) 173 which generate bias voltages, ICTL and /ICTL according to the count value and complement count value (generated by inverter 175), respectively. Thus, as the count value is incremented, the bias voltage ICTL is increased (increasing the gain of differential amplifier 1632) and bias voltage /ICTL is decreased (decreasing the gain of differential amplifier 1631), thereby shifting the phase of the output clock signal toward phase vector VB and away from phase vector VA.
Because of the high impedance load driven by the DACs 173 (i.e., the gate terminals of biasing transistors 1651 and 1652), several cycles of the reference clock signal are typically needed for the DAC to settle and, therefore, for the mix control signal to become valid. This is a significant disadvantage of the mixer 141, as a relatively long time is typically required to perform a phase locking operation in which numerous successive phase steps are needed to reach phase lock. Also, the ability to rapidly switch between phase offsets is limited by the DAC settling time.
The presence of the DPSS-to-CMOS converter 143 at the mixer output (see FIG. 2) presents another problem. Referring to FIG. 4, which illustrates a prior art CMOS-to-DPSS converter 127, it can be seen that the DPSS-level signals used within the reference loop 121 and mixers 141 and 149 of FIG. 2 are generated by pulling down the drain terminals of transistors 183 of a differential amplifier 181 according to the states of a differential CMOS input signals, INC and /INC. In order to produce linear conversion from CMOS to DPSS signaling levels, it is desirable for the current drawn by the biasing transistor 185 (controlled by bias voltage VBIAS) to be as constant as possible. Accordingly, the minimum signal swing of the DPSS signals are constrained to be at least high enough to maintain the biasing transistor 185 in the linear region of operation (i.e., in saturation). Consequently, when a CMOS input signal is high, the corresponding DPSS signal is pulled down to a signal level that is substantially above the ground potential, and when the CMOS input signal is low, the DPSS signal is pulled up to the supply voltage level, VDD. That is, as shown in FIG. 5, the DPSS signal swing is asymmetric with respect to the midpoint of the CMOS signal swing (i.e., VDD/2).
The asymmetric swing of the DPSS signal relative to CMOS signal swing tends to complicate the return conversion from DPSS to CMOS signaling levels. FIG. 6 illustrates a prior art DPSS-to-CMOS converter circuit that receives complementary differential input DPSS signals, INDPSS and /INDPSS, and that outputs a single-ended CMOS output signal, OUTC. As INDPSS goes high, transistor 201 is switched on, resulting in current I1 through transistor 205. Transistor 205 is coupled in a current mirror configuration with transistor 207, so that current I1 flows through transistor 207 and also through diode-configured transistor 209. Transistor 209 is coupled in a current mirror configuration with transistor 211, so that transistor 211 is switched on, thereby pulling output signal, OUTC, to ground. While INDPSS is high, /INDPSS is low, so that transistor 203 is switched off, thereby switching off transistors 213 and 215. Thus, when INDPSS is high, the output signal is pulled low by the switching on of transistors 201, 205, 207, 209 and then 211. By contrast, when INDPSS is low and /INDPSS is high, transistors 203, 213 and 215 are switched on to pull up the output signal, OUTC, to the supply voltage. Thus, five transistors change state in sequence to pull the output signal low and only three transistors change state to pull the output signal high. Consequently, the output signal tends to transition more slowly in response to a low-to-high transition of the DPSS input signal than in response to a high to low transition of the DPSS input signal. That is, the conversion from DPSS to CMOS signaling levels tends to introduce duty cycle distortion to an otherwise distortion free DPSS clock signal. Duty cycle correction circuits may be added to correct the duty cycle distortion, but, at least in the architecture of FIG. 2, such circuits need to be added not only in the mix loop 123, but also within sampling clock generator 125 to avoid phase error due to propagation delay through the duty cycle correction circuit. Also, because of the process dependent nature of the DPSS to CMOS converter (and ensuing duty cycle distortion circuit), the propagation delays through the converter tend to be difficult to match between the converter 151 in the sample clock generator 125 and the converter 143 within the mix loop 123, thereby introducing a potential source of phase error in the sampling clock. Duty cycle correction circuits, if included, may introduce further phase error. Also, while only two DPSS-to-CMOS converters 143 and 151 are shown in the architecture of FIG. 2, it is often necessary to convert the DPSS-level phase vectors generated by the reference loop 121 to CMOS levels for exportation to the mixers 141 and 149, then convert back from CMOS to DPSS signaling levels at the front end of the mixers. Such conversions may introduce further duty cycle distortion and phase error in the sampling clock.